I. Field of the Disclosure
The technology of the disclosure relates generally to computer memory systems, and particularly to memory controllers in computer memory systems for providing central processing units (CPUs) with a memory access interface to memory.
II. Background
Microprocessors perform computational tasks in a wide variety of applications. A typical microprocessor application includes one or more central processing units (CPUs) that execute software instructions. The software instructions instruct a CPU to fetch data from a location in memory, perform one or more CPU operations using the fetched data, and generate a result. The result may then be stored in memory. As examples, this memory can be a cache local to the CPU, a shared local cache among CPUs in a CPU block, a shared cache among multiple CPU blocks, or main memory of the microprocessor.
In this regard, FIG. 1 is a schematic diagram of an exemplary system-on-a-chip (SOC) 10 that includes CPU-based system 12. The CPU-based system 12 includes a plurality of CPU blocks 14(1)-14(N) in this example, wherein ‘N’ is equal to any number of CPU blocks 14 desired. Each CPU block 14(1)-14(N) contains two CPUs 16(1), 16(2) and a shared level 2 (L2) cache 18(1)-18(N), respectively. A shared level 3 (L3) cache 20 is also provided for storing cached data that is used by any of, or shared among, each of the CPU blocks 14(1)-14(N). An internal system bus 22 is provided that allows each of the CPU blocks 14(1)-14(N) to access the shared L3 cache 20 as well as other shared resources. Other shared resources that can be accessed by the CPU blocks 14(1)-14(N) through the internal system bus 22 can include a memory controller 24 for accessing a main, external memory (e.g., double-rate dynamic random access memory (DRAM) (DDR)), peripherals 26, other storage 28, an express peripheral component interconnect (PCI) (PCI-e) interface 30, a direct memory access (DMA) controller 32, and an IMC 34.
As CPU-based applications executing in the CPU-based system 12 in FIG. 1 increase in complexity and performance, the memory capacity requirements of the shared L2 cache 18 and the shared L3 cache 20, and external memory accessible through the memory controller 24 may also increase. However, providing additional memory capacity in a CPU-based system increases costs and area needed on for memory on an integrated circuit. For example, if a CPU-based system, such as the CPU-based system 12 in FIG. 1, where provided in a SOC, adding additional memory capacity may increase the SOC packaging. Data compression may be employed to increase the effective memory capacity of a CPU-based system without increasing physical memory capacity. However, data compression can reduce CPU memory access times and thus decrease CPU performance, because data is stored in compressed form and must then be uncompressed during memory accesses.
Thus, it would be desirable to increase memory capacity of a CPU-based system while mitigating an increase in physical memory size as complexity and performance requirements of CPU-based applications increase, while also minimizing the impact on CPU performance.